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The need for 1394 and other next-generation network topologies and protocols is driven by the rapidly growing need for mass information transfer. Typical LANs and WANs simply cannot provide cost-effective connection capabilities nor do they easily support guaranteed bandwidth for "mission critical" applications. Additionally, parallel high-speed communications such as SCSI are not suited to long distances and do not support live connect/disconnect, making reconfiguration time-consuming. Other factors driving next generation protocols such as 1394 include the need for reliability, durability and universal interconnection.

The 1394 standard is a transaction-based packet technology for cable- or backplane-based environments. Both chassis and peripheral devices can use this technology. The 1394 serial bus is organized as if it were memory space interconnected between devices, or as if devices resided in slots on the main backplane. Device addressing is 64 bits wide, partitioned as 10 bits for network Ids, 6 bits for node Ids and 48 bits for memory addresses. The result is the capability to address 1023 networks of 63 nodes, each with 281 terabytes of memory.  Memory-based addressing, rather than channel addressing, views resources as registers or memory that can be accessed with processor-to-memory transactions. Each bus entity is termed a "node," to be individually addressed, reset and identified. Multiple nodes may physically reside in a single module, and multiple ports may reside in a single node.  

Some key features of the 1394 topology are multi-master capabilities, live connect/disconnect (hot plugging) capability. vender less cabling connectors on interconnect cabling and dynamic node address allocation as nodes are added to the serial chain. Another feature is that transmission speed is scalable from approximately 100 Mbps to 400 Mbps.

Each node also acts as a repeater, allowing nodes to be chained together to form a tree topology. Due to the high speed of 1394, the distance between each node or hop should not exceed 4.5m and the maximum number of hops in a chain is 16, for a total maximum end-to-end distance of 72m. Cable distance between each node is limited primarily by signal attenuation. An inexpensive cable with 28-gauge signal pairs can be up to 4.5 meters long. 

The most widely separated nodes must have 16 or fewer cable hops between them. This gives an end-to-end distance of 72 to 224 meters.

The only restriction on the cable topologies is that a maximum of 63 nodes can be connected in a simple no-loops tree with a 00 span of 16 or fewer hops. The cable environment uses a X three-pair shielded cable and a miniature connector to carry transmit/receive data as well as to source or sink power (between 8 and 40 Vdc at no more than 1.5 A). A unique feature of the 1394 cable version is the distribution of power through the cable for operation of the transceiver's repeating functions even if the node power is off.

The cable-based physical interface uses DC-level line states for signaling during initialization and arbitration. The backplane environment uses dominate mode addresses for arbitration and does not have the initialization requirements of the cable environment because the topology does not contain repeaters. The physical addresses may be set by the slot position within the chassis. Due to the differences, a backplane-to-cable bridge is required to connect these two environments. Because of the commonality of the link and other layers, this bridge is quite simple, needing only to core and re-clock the packets.

The signals transmitted on both the cable and backplane environments are NRZ with Data-Strobe (DS) encoding. DS encoding allows only one of the two signal lines to change each data bit period, essentially doubling the jitter tolerance with very little additional circuitry overhead in the hardware. DS encoding is licensed from SGS-Thomson/INMOS and is used in other serial interfaces such as P1355 Protocol

Both asynchronous and isochronous data transfers are supported. The asynchronous format transfers data and transaction layer information to an explicit address. The isochronous format broadcasts data based on channel numbers rather than specific addressing.  Isochronous packets are issued on the average of each 125 in support of time-sensitive applications.  Providing both asynchronous and isochronous formats on the same interface allows both non-real-time critical applications-such as printers, STGTs and scanners-and real-time critical applications-such as video and audio-to operate on the same bus.

The tree topology is resolved during a sequence of events triggered each time a new node is added or removed from the network. This sequence starts with a bus reset phase, where all previous information about a topology is cleared. The tree ID sequence determines the actual tree structure. During the tree ID process, each node is assigned an address and a root node is dynamically assigned, or it is possible to force a particular node to become the root.   After the tree is formed, a self-ID phase allows each node on the network to identify itself to all other nodes. After all of the information has been gathered on each node, the bus goes into an idle state waiting for the beginning of the standard arbitration process.

An additional feature is the ability of transactions at different speeds to occur on a single device medium (for example, some devices can communicate at 100 Mbps while others communicate at 200 Mbps and 400 Mbps). Use of multispeed transactions on a single 1394 serial bus requires consideration of each node's maximum capabilities when laying out the connections to ensure that the path between two higher-speed nodes is not blocked by a device with base-rate abilities.

Conclusion
The 1394-1995 serial-bus has the bandwidth capacity to displace most other peripheral connection communication methods in use today, including Centro nix parallel, RS232, SCSI and Apple's Desktop Bus, and consolidate them into a unified high-performance serial bus. As the technology is developed and deployed, new interfaces such as direct connect video I/O can  find a home where the physical limitations of today's interconnect prevent wide deployment.  The serial bus' memory space addressing is a perfect fit for "slotless" systems such as PDAs. Finally, the "hot plugging," power sourcing and dynamic reconfiguration abilities make 1394 a user-friendly environment. The features of 1394 will allow plugging in a computer expansion system as easily as plugging into AC power, providing communications on demand without having to shutdown and reconfigure each time an I/O device is added or removed. 

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• Real-time data transfer for multimedia applications 100, 200, & 400Mbits/s data rates today; 800 Mbits/s and multi-Gbits/s upgrade path

• Live connection/disconnection without data loss or interruption

• Automatic configuration supporting "plug and play"

• Free form network tool allowing mixing branches and daisy-chains

• No separate line terminators required

• Guaranteed bandwidth assignments for real-time applications

• Common connectors for different devices and applications

• Compliant with IEEE 1394 High Performance Serial Bus standar

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The Bus Manager must collect the self-id packets and create the topology and speed maps from them. Depending on the FIFO sizes, the collection of the self-id packets can be a problem if the bus has a lot of nodes. See section 8.4.2.5 of the IEEE 1394-1995 standard for determination of the Bus Manager and section 8.3.1.6 for responsibilities of a Bus Manager.

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Only the Bus Manager (or IRM if no Bus Manager is on the bus) may force a node to become root. If there is no IRM capable node on the bus, then the 1394 node described should not send isochronous packets.

The only reason a node would not want to be root is that it does not want to be Cycle Master. See paragraph 8.4.2.6 of the IEEE 1394-1995 standard to understand how the Cycle Master is selected.

The Bus Manager (or IRM if a bus manager is not present) will find a node capable of being Cycle Master. It will then send a PHY configuration packet to force that node to become root and cause a bus reset. It will then set the cmstr bit in the STATE_CLEAR register of the root node to turn on the Cycle Master. Of course a node that is IRM capable will also be Cycle Master capable and may make itself root.

There is no way for a node to cause itself not to be root. There is a way to force a node to become root by setting the RHB (Root Holdoff Bit) with a PHY configuration packet and then initiating a bus reset. If your node always becomes root, then for some reason your PHY is slower than the other PHYs on the bus.

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